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A high-speed 128-kb MRAM core for future universal memory applications

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15 Author(s)
J. DeBrosse ; IBM Microelectron., Essex Junction, VT, USA ; D. Gogl ; A. Bette ; H. Hoenigschmid
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A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-μm VDD=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-μm2 one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:39 ,  Issue: 4 )