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Repeater scaling and its impact on CAD

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4 Author(s)
Saxena, P. ; CAD Res., Intel Corp., Hillsboro, OR, USA ; Menezes, N. ; Cocchini, P. ; Kirkpatrick, D.A.

We study scaling in the context of typical block-level wiring distributions, and identify its impact on the design process. In particular, we study the implications of exponentially increasing repeater and clocked repeater counts on the algorithms and methodologies used for physical synthesis and full-chip assembly, showing that mere capacity scaling of current algorithms and methodologies is insufficient to handle the new challenges. Finally, we suggest a few approaches to tackle these challenges by constructing a case for abstract fabrics.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:23 ,  Issue: 4 )

Date of Publication:

April 2004

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