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Testbenches play one of the most important roles in simulation-based design verification. Given a simulation scenario, a testbench provides specific vectors to simulate the design, then collects responses from the design to monitor whether the simulation has satisfied the scenario. The major bottleneck in writing testbenches is generating valid simulation vectors. Many current automatic-vector-generation methods focus on exploring a design's state space. Due to memory or runtime limitations, these methods cannot keep up with the rapid growth of design complexity. We propose a novel algorithm based on the divide-and-conquer paradigm that helps these methods decompose the design's complexity. The algorithm uses a partitioning method that recursively divides a design into smaller, more manageable components. Other approaches handle the divided components while maintaining the entire design's proper functioning. Random simulation generates sets of simulation vectors by randomly assigning the logic values to the design's primary inputs (Pis) one cycle at a time. Unlike random simulation, which uses only a single trace, symbolic solvers attempt to simultaneously enumerate all possible primary inputs to explore the entire state space. They typically use binary decision diagrams (BDDs) or satisfiability (SAT) solvers as their core engine.