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This paper proposes an efficient hardware architecture to accelerate adaptive deblocking filter of H.264/A VC video coding. Compact data access unit, line-of-pixel (LOP) is defined in this paper. Line-of-pixel and build-in data buffer are employed to simplify data exchange between deblocking filter and outside data memory. Edge filter, which is designed to process each group of pixels on both sides of one edge, is kernel of deblocking filter. It is implemented in multiple parallel pipelines to increase efficiency. By carefully design, the proposed deblocking filter can be embedded in general-purpose processor or DSP to support special instructions for acceleration of software codec. This filter also can be used to full hardware H. 264/A VC codec.