Skip to Main Content
A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described. The circuit is fully compatible with standard digital CMOS technology. A modified folding block implemented without resistor contributes to a small chip area 475 μm × 526 μm. Offset averaging reduces the input capacitance. Fully-differential and open-loop analog circuitry is used to achieve high speed. The 200-Ms/s 8-bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18 μm 3.3V CMOS technology.