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An embedded 200-Ms/s 8-bit 177mW folding and interpolating CMOS ADC in 0.25-mm2

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4 Author(s)
Chen Cheng ; ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China ; Wang Zhaogang ; Ren Junyan ; Xu Jun

A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described. The circuit is fully compatible with standard digital CMOS technology. A modified folding block implemented without resistor contributes to a small chip area 475 μm × 526 μm. Offset averaging reduces the input capacitance. Fully-differential and open-loop analog circuitry is used to achieve high speed. The 200-Ms/s 8-bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18 μm 3.3V CMOS technology.

Published in:

ASIC, 2003. Proceedings. 5th International Conference on  (Volume:1 )

Date of Conference:

21-24 Oct. 2003