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A 1.8-V 64-kb four-way set-associative CMOS cache memory using fast sense amplifier and split dynamic tag comparators

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This paper reports a 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18 μm 1.8 V 1P6M logic CMOS technology. This cache is designed for a 32-b RISC microprocessor. Effective latency of 3.4 ns and power consumption of 190 mW at 263 MHz are obtained at a supply voltage of 1.8 V. This performance is achieved by using high speed circuit design techniques such as modified high speed current-mode sense amplifier and split dynamic tag comparators.

Published in:

ASIC, 2003. Proceedings. 5th International Conference on  (Volume:1 )

Date of Conference:

21-24 Oct. 2003