Design and implementation of a reconfigurable architecture for DSP

To accelerate the execution of most DSP (Digital Signal Processing) algorithms such as FFT, FIR, Vector operations, while keeping the flexibility of the chip, a reconfigurable architecture (named ReDAr) for DSP is proposed and implemented, and finally will be applied to the Radar system of Automatic Navigation Equipment. By analyzing these algorithms, the structure of Reconfigurable Processing Element (RPE), the Crossbar interconnect network, the Memory organization, the host controlling strategy, and the data sequencing scheme of the architecture are conceived, and parts of them, including the RPE, Crossbar, data sequencer, are reconfigurable. After configuration, it can be interconnected into a parallel and pipelined framework, closely matching the algorithms and like a dedicated hardware. By simulation, the performances of these algorithms mapped onto this architecture are comparative to algorithm-specific chips in market, and satisfy the requirement of the targeted application.