By Topic

A reconfigurable architecture of high performance embedded DSP core with vector processing ability

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Jie Chen ; Microelectron. R&D Center, Chinese Acad. of Sci., Beijing, China ; Chaoxin Zhou ; Zhibi Liu ; Liang Han
more authors

System-on-a-chip (SOC) is the best solution to meet with the requirement of the state-of-the-art electronic products such as portable mobile terminals and digital cameras in the terms of performance, cost and reliability. To design a high performance SOC chip with high flexibility, embedded DSP or CPU cores are essential component. In this paper, starting with a briefly review on the major features of main-stream DSP processors developed since 1980's, we discuss the special requirement in design of embedded DSP cores, and present a new reconfigurable parallel architecture of high performance embedded DSP core with vector processing ability for media and mobile communication signal processing.

Published in:

ASIC, 2003. Proceedings. 5th International Conference on  (Volume:1 )

Date of Conference:

21-24 Oct. 2003