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Browse Conference Publications > ASIC, 2003. Proceedings. 5th ... Help

A synchronizing method for designing VLSI chip's P/G topology with noise and reliability considerations

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3 Author(s)
Jing Li ; Univ. of Electron. Sci. & Technol. of China, Chengdu, China ; Chunhui Li ; Juebang Yu

The reliability and optimum result of P/G nets routing method can affect area optimization and electricity performance of whole CMOS chip. Based on the analysis of noise uniform distribution and reliability of module operation, in this paper, we present a synchronizing method for optimum design of power and ground topology. Experimental results demonstrate the better characteristic of noise uniform distribution and operating reliability.

Published in:
ASIC, 2003. Proceedings. 5th International Conference on  (Volume:1 )

Date of Conference: 21-24 Oct. 2003

Page(s):
258 - 261 Vol.1
ISSN :
1523-553X
Print ISBN:
0-7803-7889-X
INSPEC Accession Number:
8015772
Digital Object Identifier :
10.1109/ICASIC.2003.1277537
Product Type:
Conference Publications

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