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A new incremental placement approach is described in this paper. The obtained timing information drives an efficient net-based placement technique, which dynamically adapts the net weights during successive placement steps. Several methods to combine timing optimization and congestion reducing together are proposed to achieve good result without increasing the computational load. Cells on critical paths are replaced according to timing and congestion constraints. Experimental results show that our approach can efficiently reduce cycle time and enhance route ability. The max path delay is reduced about 13% on an average after incremental placement on wirelength optimized circuits.
ASIC, 2003. Proceedings. 5th International Conference on (Volume:1 )
Date of Conference: 21-24 Oct. 2003