A novel SAD computing hardware architecture for variable-size block motion estimation and its implementation with FPGA

This paper presents a new hardware architecture that calculates SAD for variable block-size motion estimation (VBSME). The proposed architecture with a 16×1-PE array, a 4-stage adder tree and two flexible register arrays supports 16×16, 16×8, 8×8, 8×4, 4×8, and 4×4 block's SAD calculation. The architecture can be used in the encoder that supports the enhanced motion estimation with variable block size in the MPEG-4 AVC (advanced video coding) and the emerging H.264 standard. Our design was described in Verilog-HDL and implemented in a Altera FPGA APEX20K with a clock frequency of 120MHz allowing the processing of 29296 16×16 per search area.