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A system on a chip design of digital camera processor for mega-pixel CCD digital camera is proposed. The processor integrates pipelined real-time digital image processor, JPEG codec and AE/AWB/AF controller. It supports 8-bit MCU and synchronous DRAM and provides interfaces to CCD, LCD, TV, PCMCIA, USB and EPP. The processor works in view-find, snapshot, playback and transfer modes. The snapshot speed is 5fps at 1.3M pixels and the view-find speed is fps. The chip is fabricated with 0.25 μm CMOS technology and has 200K logic gates with 12KB internal memory. The chip area is 25mm2 and the power consumption is 500mW at 54MHz system clock.
ASIC, 2003. Proceedings. 5th International Conference on (Volume:2 )
Date of Conference: 21-24 Oct. 2003