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A parallel architecture for VLSI implementation of FFT processor

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1 Author(s)
Yongjun Peng ; Dept. of Electron. Sci. & Technol., Univ. of Sci. & Technol. of China, Hefei, China

In this paper, we propose an implementation method with high throughput for a single-chip 4096 complex point FFT. In order to increase transform speed, a parallel FFT architecture has been used. There are eight parallel basic processing modules in the entire FFT chip, which can work at the same time independently. The proposed architecture can compute 4096 complex point forward or inverse FFT in real time with up to 320 MHz sampling frequency, and applied widely in high-speed signal processing.

Published in:

ASIC, 2003. Proceedings. 5th International Conference on  (Volume:2 )

Date of Conference:

21-24 Oct. 2003