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A compiled-code hardware accelerator for circuit simulation

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1 Author(s)
Lewis, D.M. ; Dept. of Electr. Eng., Toronto Univ., Ont., Canada

Describes the application of compiled-code techniques to the design of a hardware accelerator for circuit simulation, offering a speedup by a factor of up to 4400 compared with a software circuit simulator running on a Sun-3/60 workstation. The preprocessing algorithms are designed for high speed, so overall simulation time is improved by a factor of up to 560. Compiled-code hardware accelerators offer several advantages. The hardware is simpler than fully hard-wired accelerators. The simplicity of the hardware makes it possible to track advancing implementation technology and to maintain the performance advantage as technology improves. The simulation algorithm is implemented in software, making it possible to implement and maintain multiple algorithms without hardware modifications. The hardware can be used efficiently, since compiled-code techniques can eliminate or statically perform operations that would be repeatedly performed in other hard-wired implementations

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:11 ,  Issue: 5 )