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Systematic VHDL code generation using pipeline operations produced by high level synthesis

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2 Author(s)
P. Arato ; Dept. of Control Eng. & Inf. Technol., Budapest Univ. of Tech. & Econ., Hungary ; T. Kandar

We present a method for systematic VHDL code generation from a data-flow representation. In such cases, a methodology is needed that yields a hardware description, which are synthetized and mapped into an FPGA. This procedure speeds up the development of the prototype, reduces the time-to-market, and helps the logic and timing simulation.

Published in:

Intelligent Signal Processing, 2003 IEEE International Symposium on

Date of Conference:

4-6 Sept. 2003