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On-chip communication architectures for reconfigurable System-on-Chip

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2 Author(s)
Lee, A.S. ; Sch. of ITEE, Queensland Univ., Brisbane, Qld., Australia ; Bergmann, N.W.

On-chip communication architectures can have a great influence on the speed and area of System-on-Chip designs, and this influence is expected to be even more pronounced on reconfigurable System-on-Chip (rSoC) designs. To date, little research has been conducted on the performance implications of different on-chip communication architectures for rSoC designs. The paper surveys existing solutions for SoC and analyses the suitability for rSoC application. It also describes work in progress on implementation of a simple serial bus and a packet-switched network, as well as a methodology for quantitatively evaluating the performance of these interconnection structures in comparison to conventional buses.

Published in:

Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on

Date of Conference:

15-17 Dec. 2003