By Topic

A fully parallel CMOS analog median filter

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
A. Diaz-Sanchez ; Electron. Dept., Instituto Nacional de Astrofisica, Opt. y Electron., Puebla, Mexico ; Jaime Ramirez-Angulo ; A. Lopez-Martin ; E. Sanchez-Sinencio

A fully integrated CMOS implementation of a continuous-time analog median filter is presented. The median filter uses two compact analog circuits as building blocks to implement the variable delay and median detection. Median detectors are based on current saturating transconductance comparators, while the time delay is implemented using first-order all-pass filters. Both circuits allow modular expansion for the implementation of large median filter array processors. Based on these blocks, a new fast technique for parallel image processing is presented. It is shown that an image of 91×80 pixels can be processed in less than 8 μs using an array of median filter cells. Experimental results of a test chip prototype in 2-μm CMOS MOSIS technology are presented.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:51 ,  Issue: 3 )