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Continuous-time filter design optimized for reduced die area

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4 Author(s)
Myers, C. ; Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA ; Greenley, B. ; Thomas, D. ; Un-Ku Moon

A method for distributing capacitor and resistor area to optimally reduce die area in a given continuous-time filter design while maintaining the filter's designed signal-to-noise ratio (SNR), frequency response, and topology is discussed. To do this, a basic linear programming algorithm is developed from derived circuit cost and constraint functions. Among the three major filter types of fifth-order under comparison, maximum combined capacitor and resistor die area savings of 21% results for the Butterworth filter. An alternative approach where the SNR is optimized for a given die area is also presented. Maximum improvement of the fifth-order Butterworth filter for this approach is 1.2 dB.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:51 ,  Issue: 3 )

Date of Publication:

March 2004

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