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Compact model generation for on-chip transmission lines

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3 Author(s)
Taeik Kim ; Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA ; Xiaoyong Li ; D. J. Allstot

An approach for the fast and accurate generation of compact distributed circuit models for on-chip transmission lines on lossy silicon substrates is presented. Using a novel ABCD matrix partitioning procedure, accurate distributed circuit models are extracted from scattering parameters obtained from measurements and calibrated full-wave electromagnetic simulations for a small set of transmission-line geometries spanning ranges of design parameter values. A feedforward artificial neural network is trained using the extracted results, and applied to generate accurate compact models for arbitrary values within the bounds of the training ranges. Consequently, the model generation time is greatly reduced compared to conventional approaches by exploiting the interpolation capabilities of the neural network. The compact model generator is fully compatible with HSPICE and SPECTRE-RF and is easily incorporated into parasitic-aware RF circuit design and optimization tools.

Published in:

IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:51 ,  Issue: 3 )