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A formal description of an implementation under test (IUT), such as its VHDL behavior description, is required to automatically generate feasible test sequences for the IUT. Although finite-state machines (FSMs) can be used to describe the control structures of communication protocols, the data portion can only be modeled by extended finite-state machines (EFSMs). However, infeasible paths due to the conflicts among the condition and action variables of EFSMs complicate the test generation process. We introduce a method enabling the automatic generation of realizable test sequences from a class of EFSMs. Algorithms to detect and eliminate conflicts caused by the interdependences among the variables of a class of EFSM models are presented. After all conflicts are eliminated from the EFSM graph, the existing FSM-based automated test generation methods can be used to generate feasible test sequences. Recently, these algorithms have been implemented as a software package called INDEEL. This methodology is applied to generate feasible tests for protocols such as ACA and MIL-STD 188-220. Current applications include IETF protocols and ASAP.