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A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip

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2 Author(s)
Zimmer, H. ; Darmstadt Univ. of Technol., Germany ; Jantsch, A.

The reliability of a network-on-chip will be significantly influenced by the reliability of the switch-to-switch connections. Faults on these buses may cause disturbances on multiple adjacent wires, so that errors on these wires can no longer be considered as statistically independent from one another, as it is expected due to deep submicron effects. A new fault model notation for buses is proposed which can represent multiple-wire, multiple-cycle faults. An estimation method based on this notation is presented which can accurately predict error probabilities. This method is used to examine bus encoding schemes. Finally, an encoding scheme for four quality-of-service classes is proposed which can be dynamically selected for each packet.

Published in:

Hardware/Software Codesign and System Synthesis, 2003. First IEEE/ACM/IFIP International Conference on

Date of Conference:

1-3 Oct. 2003

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