Architecture and synthesis for multi-cycle on-chip communication

There are two important infection points in the development of deep submicron (DSM) process technologies. The first point is when the average interconnect delay exceeds the gate delay, which happened during mid 1990s and led to the so-called timing closure problem. The second point is when single-cycle full chip synchronization is no longer possible, which is about to happen soon. It can be shown that, even with the aggressive interconnect optimization techniques (e.g., buffer insertion and wire-sizing), 5 clock cycles are still needed to go from corner-to-corner for the die of 28.3 mm /spl times/ 28.3 mm in the 0.07 /spl mu/m technology generation, assuming a 5.63 GHz clock by 2006 predicted in ITRS'01 (2001). This clearly suggests that multi-cycle on-chip communication is a necessity in multi-gigahertz synchronous designs. However, it is not supported in the current design tools and methodologies, as most of these implicitly assume that full chip synchronization in a single clock cycle is feasible. Our contributions are as follows: (i) we propose a regular distributed register (RDR) microarchitecture which offers high regularity and direct support of multi-cycle communication; (ii) we develop a set of novel architectural synthesis algorithms to efficiently synthesize behavior-level designs onto the RDR architecture.