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CMOS-compatible lateral bipolar transistor for BiCMOS technology. I. Modeling

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4 Author(s)
N. Akiyama ; Hitachi Ltd., Ibaraki, Japan ; A. Tamba ; Y. Wakui ; Y. Kobayashi

A CMOS-compatible lateral bipolar transistor having neither an epitaxial layer nor n+-buried layers is proposed. The simulation indicates that the BiCMOS gate delay time shows a weak dependence on the metallurgical base width WB, (and hence on fTmax, since fT∝1/ WB2) and strong dependence on the effective base width WB(eff), where WB(eff) nearly equals the distance between the emitter and the n+ collector, dE-C. This is because bipolar transistors in BiCMOS circuits are operated in high-level injection during the switching transient. Therefore, it is possible to build a high-speed BiCMOS gate using lateral bipolar devices with short dE-C. The transistor has a structure similar to that of an n-channel MOSFET. The emitter and collector are formed simultaneously and self-aligned to a polysilicon base electron like the source and drain in a MOSFET

Published in:

IEEE Transactions on Electron Devices  (Volume:39 ,  Issue: 4 )