By Topic

Implementation of low power fast Fourier transform

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Jamal, H. ; Univ. of Eng. & Technol., Taxila, Pakistan ; Shabbir, A. ; Qadeer, I.

This paper provides a novel low power high-speed computation of the fast Fourier transform (FFT) of complex floating-point data. This is achieved by designing the FFT butterfly operator to have reduced switching activity and lesser hardware. Normally the calculation of a butterfly requires eight real multiply and eight real addition operations. The proposed architecture requires only four real multiply and six real additions to compute the butterfly operator. Comparing the switching activity, a Two-fold reduction of switching activity has been observed at the input of the multiplier in proposed design. Dadda tree has been used for partial product reduction for its regularity in structure and optimal number of computational elements. The final two rows of partial products are reduced using carry save adder because of its high speed. The proposed design also takes relatively lesser number of clock cycles.

Published in:

Communications, 2003. APCC 2003. The 9th Asia-Pacific Conference on  (Volume:2 )

Date of Conference:

21-24 Sept. 2003