By Topic

An architecture for affine motion estimation in real-time video coding

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
A. Girotra ; Div. of Multimedia, Sanyo LSI Technol. India Pvt. Ltd., Bangalore, India ; S. Johar ; D. Ghosh ; I. Chakrabarti

With the ever-increasing demand for real-time video applications, a dedicated and efficient architecture for motion estimation has become a necessity. In this paper, we present an architecture for affine motion estimation which meets the real-time application requirements. The architecture employs a modular memory structure for efficient pipelined parallel implementation of affine motion estimation using the one-dimensional hierarchical search (IDHS) algorithm. Implementation results in terms of the number of clock cycles and PSNR values demonstrate the efficiency of the proposed architecture.

Published in:

Communications, 2003. APCC 2003. The 9th Asia-Pacific Conference on  (Volume:1 )

Date of Conference:

21-24 Sept. 2003