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In this research paper, a novel method of fabricating 3D-stacked modules using a silicon carrier that can integrate known good dice, with testable features and integrated cooling solution is presented. The backbone of this silicon based system in package (SiP) is the fabrication of silicon carriers with through hole conductive interconnects. Process development, issues and limitations of the novel method to fabricate silicon carriers with solder and Cu conductive interconnects are discussed in detail. Through holes in silicon wafer have been demonstrated with conventional low cost batch processing wet etch and high aspect ratio DRIE methods to address coarse pitch and fine pitch applications respectively. Ultra thin flip chip device with daisy chain are fabricated and are attached to the silicon carriers by conventional flip chip processes, forming a stack. Individual stacks are vertically integrated to form three dimensional stacked modules. A complete three dimensional stacked module has been fabricated with three individual stacks. The fabricated stack modules have been subjected to JEDEC reliability tests and the results are discussed.
Date of Conference: 10-12 Dec. 2003