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Improving cache locality with blocked array layouts

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2 Author(s)
Athanasaki, E. ; Sch. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Greece ; Koziris, N.

Minimizing cache misses is one of the most important factors to reduce average latency for memory accesses. Tiled codes modify the instruction stream to exploit cache locality for array accesses. Here, we further reduce cache misses, restructuring the memory layout of multidimensional arrays, that are accessed by tiled instruction code. In our method, array elements are stored in a blocked way, exactly as they are swept by the tiled instruction stream. We present a straightforward way to easily translate multidimensional indexing of arrays into their blocked memory layout using simple binary-mask operations. Indices for such array layouts are easily calculated based on the algebra of dilated integers, similarly to morton-order indexing. Actual experimental results, using matrix multiplication and LU-decomposition on various size arrays, illustrate that execution time is greatly improved when combining tiled code with tiled array layouts and binary mask-based index translation functions. Simulations using the Simplescalar tool, verify that enhanced performance is due to the considerable reduction of total cache misses.

Published in:

Parallel, Distributed and Network-Based Processing, 2004. Proceedings. 12th Euromicro Conference on

Date of Conference:

11-13 Feb. 2004