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This paper describes a new approach for timing analysis in general and, more specifically, for statistical timing analysis. A methodology based upon the utilization of the design hierarchy for circuit partitioning and building of the simulation hierarchy was developed. The logic and timing behaviors of the blocks resulting from the partitioning are dissociated and modeled separately. The logic model is represented by an equivalent finite state machine while an automated characterization process extracts the timing data from multiple circuit simulations in order to build a parametric timing model. These models provide the basis of an event-driven hierarchical timing simulator which can be used as a stand-alone tool but also as a front end for statistical timing analyses. Both the nominal and the statistical simulators have been implemented within STAT! (Statistical Timing Analysis Tool), and the results obtained for a few test cases are presented here.