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Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI

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4 Author(s)
Tat-Kwan Yu ; Coordinated Science Laboratory and Department of Electrical and Computer Engineering, University of Illinois, Urbana, IL, USA ; Sung Mo Kang ; I. N. Haji ; T. N. Trick

A major cost in statistical analysis occurs in repeated system simulation as system parameters are varied. To reduce this cost, the system performances are approximated by regression models in terms of critical system parameters. These models are then used to predict the performance variations and parametric yield. This paper presents a systematic and computationally efficient method for deriving regression models of MOS VLSI circuit performances that can be used to estimate the parametric yield. This method consists of four fundamental steps: simulation point selection, model fitting and validation, model improvement, and parametric yield estimation. An average mean-squared error criterion is used to select an optimal set of points in the design space for circuit simulations, and the adequacy of the fitted regression model is checked rigorously. It will be shown through examples that accurate statistical performance models and parametric yield estimate for MOS VLSI can be derived by using four or five critical device parameters and a small number of circuit simulations.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:6 ,  Issue: 6 )