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VLSI Layout Compaction with Grid and Mixed Constraints

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2 Author(s)
Jin-Fuw Lee ; IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA ; Tang, D.T.

We investigate the modeling and solution techniques of VLSI layout compaction using the constraint graph approach under various practical design considerations. In particular, we extend the graph method to the compaction of VLSI layout with mixed grid constraints in addition to the usual minimum- and maximum-type constraints. This is a mixed integer problem. We show that it can be solved by the search of effectively longest paths, and a fast algorithm is presented

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:6 ,  Issue: 5 )