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This paper proposes a new layout method for high-speed VLSI circuits in single-poly and double-metal MOS technology. With emphasis on the speed performance, our Metal-Metal Matrix (M 3) layout method employs maximal use of metal interconnections while restricting delay-consuming polysilicon or polycide features only to form MOS transistor gates or to connect the same type of transistor gates with common input signals. M 3 layout is also amenable to submicron technology trends and existing CAD tools for single-poly and single-metal chip assembly and routing. Our layout studies indicate that M 3 is particularly appealing to high-speed dynamic CMOS circuits in view of packing density and speed performance. This new structure has not been experimented with VLSI chip fabrication yet and awaits empirical verification.