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Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations

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3 Author(s)
Rogers, W.A. ; Department of Electrical and Computer Engineering, University of Texas, Austin, TX, USA ; Guzolek, J.F. ; Abraham, J.A.

This paper presents the technique of concurrent hierarchical fault simulation, a performance model, and two hierarchical optimization techniques to enhance fault simulator performance. The mechanisms for these enhancements are demonstrated with a performance model and are validated experimentally via CHIEFS, the Concurrent Hierarchical and Extensible Fault Simulator, and WRAP, an offline hierarchy compressor. Hieararchy-based fault partitioning and circuit reconfiguration are shown to improve simulator performance to O(n log n) under appropriate conditions. A decoupled fault modeling technique permits further performance improvements via a bottom-up hierarchy compression technique where macros of primitives are converted to single primitives. When combined, these techniques have produced a factor of 180 speedup on a mantissa multiplier. The performance model indicates that the speedup should increase with circuit size.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:6 ,  Issue: 5 )