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A two-dimensional stochastic model of the global wiring of a VLSI chip in a standard-cell or sea-of-gates design style is defined; prominent in the model is the property that the probability of connecting two pins is solely a function of the distance between the cells containing them. It is also assumed that each net consists of just two pins. A lower bound is placed on the expected size of the chip with the best possible wiring. An upper bound is placed on the expected size of the chip with a trivial (all randomly-oriented "L"s) wiring scheme. If the chip size is m rows by n columns and the size of the average row is /overbar μ/ the sizes of the trivial and perfect routings, expressed as a fraction of the size of the perfect routing, approaches 0 as √2 log (n)/ /overbar μ/ It is also shown that with probability at least 1 - ∊ size increase is no more than √2 log (mn/∊/ /overbar μ/.