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The quality of the design of large-scale integrated circuits is determined by such figures of merit as silicon area, power consumption, and switching-time performance. We address here the problem of the automatic synthesis of digital circuits with the goal of achieving high-performance designs. We assume we are given an intermediate circuit representation that optimizes area and/or power. We use timing optimization techniques to improve the circuit performance, possibly at the expense of the other figures of merit. We consider general classes of digital circuits, with a given partition into registers, combinational blocks, and I/O ports. Circuit performance is related to the worst-case propagation delay of signals between two register boundaries. In this context, circuit performance optimization is equivalent to minimizing the critical path delay through the combinational circuits. We assume a multiple-level implementation of the combinational logic, by means of an interconnection of logic gates implementing arbitrary multiple-input, single-output logic functions. We consider dynamic CMOS implementation of the logic gates, operating in the domino mode. We present a global approach to timing performance optimization, which involves operations at the logic, topological, and physical level of abstraction of the circuit. In particular, at the logic level, we look for optimal structures of multiple-level combinational networks. At the topological level, we search for the optimal positions of gates or groups of gates. At the physical design level, we optimize MOS device sizes. The algorithms are described, together with their implementation and the interface to the Yorktown Silicon Compiler system, which is an automated synthesis system described in . The results of applying timing-performance optimization to a 32-bit microprocessor design are reported.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:6 , Issue: 5 )
Date of Publication: September 1987