Skip to Main Content
A new approach to the timing verification of digital designs is introduced in this paper. The approach is capable of verifying synchronous and asynchronous digital designs including self-timed asynchronous circuits . Every component in a circuit is represented by a timing description that may concurrently execute with other descriptions. Communication between and scheduling of the timing descriptions are distributed in every description and, in this approach, parallelism may be utilized with relative ease. Conventional approaches to timing verification such as SCALD , TV , and the one reported by Hitchcock  are limited to the verification of synchronous designs only. The approach has been verified through an implementation in the RDV system  at Stanford University. Descriptions of timing models of asynchronous and synchronous digital devices including a simplified AMD2903 architecture are also presented in this paper.