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This paper presents a general methodology for designing optimal test structures and their applications to characterize the process fluctuations inherent in IC manufacturing. A set of test structures, including a novel test structure, is presented in which each test structure parameter is sensitive to a minimal number of process parameters. The procedure for device parameter extraction is described. Optimal device dimensions, criteria for choosing the sample sizes of test structures, and test chips are also determined based upon statistical hypothesis testing techniques. This methodology is illustrated by an application for tuning of the statistical process/device simulator FABRICS II to a typical NMOS fabrication process.