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A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor

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3 Author(s)
Watanabe, T. ; Atsugi Electrical Communications Laboratories, NTT, Kanagawa, Japan ; Kitazawa, H. ; Sugiyama, Y.

A new parallel-processing wire-routing algorithm is presented and implemented on a parallel processor. The two main features of the parallel algorithm are the control of the path quality and the finding of a quasi-minimum Steiner tree. Both Lee's maze algorithm and the proposed algorithm are implemented on an AAP-1 two-dimensional array processor, and the performance is compared to that of software programming on a general-purpose computer. It is shown experimentally that routing by the proposed algorithm implemented on the AAP-1 is 230 times faster than a software maze router run on a 1-MIPS computer for a three-pin/net circuit on a 256 X 256 grid.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:6 ,  Issue: 2 )