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Methodology Verification of Hierarchically Described VLSI Circuits

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2 Author(s)
I. L. Bain ; Department of Electrical Engineering and Computer Science and the Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA, USA ; L. A. Glasser

The standard approach to master the complexity of designing VLSI systems is to adopt a set of rules that, when respected, are conducive to correct implementations. Any such collection of rules can be called a design methodology. Most of the effort in computer-aided VLSI methodology verification has been traditionally concentrated on geometrical DRC. This paper describes a program that checks circuit conformity to other kinds of rules. This is done at the transistor level, and most of the rules are user-selected. Two related issues are also discussed: the description of digital MOS circuits using wiring operators; and the formal description of methodologies by the designer.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:6 ,  Issue: 1 )