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Digraph Relaxation for 2-Dimensional Placement of IC Blocks

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2 Author(s)
M. J. Ciesielski ; GTE Laboratories Inc., Waltham, MA, USA ; E. Kinnen

A new graph-theoretic representation of the placement of rectangular IC blocks of arbitrary size and aspect ratio is proposed. This representation, called a relaxed digraph, provides an efficient model for two-dimensional calculations of minimum area layouts. Unlike other digraph models, the structure of the relaxed digraph represents an entire class of layout configurations derivable from a given initial placement of blocks. This model, therefore, provides greater flexibility in block placement than can be obtained from stiff digraph representations. A necessary and sufficient condition is derived for the existence of a nonoverlapping arrangement of rectangular cells in terms of the relaxed digraph representation. Based on this result, a fixed digraph representation can be selected from the relaxed digraphs that minimizes the layout area. The minimization utilizes positional constraints imposed by the relaxed digraphs and estimated routing space requirements. The area minimization is formulated as a quadratic optimization problem and solved using mathematical programming methods. The resulting modified digraph can then be used as a graph model for further calculations of a minimum area and routing-feasible layout.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:6 ,  Issue: 1 )