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Block-Level Hardware Logic Simulation Machine

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5 Author(s)
S. Takasaki ; NEC Corporation, Fuchu City, Tokyo, Japan ; T. Sasaki ; N. Nomizu ; N. Koike
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This paper describes a block-level hardware logic simulation machine. This is called a Hardware Logic Simulator (HAL). This paper first shows a block-level simulation method. Then, it overviews HAL hardware and software system configurations, and the simulation mechanism, and it estimates system performance. Finally, it discusses system applications and results. The paper also indicates that HAL has been successfully used.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:6 ,  Issue: 1 )