By Topic

ADVIS: A Software Package for the Design of Systolic Arrays

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
D. I. Moldovan ; Department of Electrical Engineering, University of Southern California, Los Angeles, CA, USA

A methodology for mapping numerical algorithms into systolic arrays is presented in this paper. This mapping is done using a transformation function which transforms the original sequential algorithm into a suitable parallel form. A program was developed to automatically generate this transformation. We consider both the case of arbitrarily large systolic arrays as well as the more realistic case of fixed-size systolic arrays requiring algorithm partitioning. An example of the algorithm is given to present the methodology and the results obtained with the program.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:6 ,  Issue: 1 )