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SPICE Simulation of SOI MOSFET Integrated Circuits

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3 Author(s)
S. Veeraraghavan ; Department of Electrical Engineering, University of Florida, Gainesville, FL, USA ; J. G. Fossum ; W. R. Eisenstadt

A five-terminal, charge-based model for the thin-film silicon-on-insulator (SOI) MOSFET is implemented in SPICE2, thereby enabling, for the first time, proper simulation and CAD of SOI MOS integrated circuits in which the unique floating-body and back-gate-bias effects can be significant. The implementation is achieved, without having to rewrite the circuit simulator, by developing a general method for incorporating new charge-based device models into SPICE2 that utilizes user-defined controlled sources (UDCS's). The utility and computing efficiency of the SOI MOSFET model implementation are demonstrated by simulating several representative SOI MOS circuits.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:5 ,  Issue: 4 )