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PLATypus (PLA Test pattern generation and logic simulation tool) is an efficient tool for large PLA's which is interfaced with other existing PLA tools such as the folding program PLEASURE  and the logic minimizer ESPRESSO II-C  developed at the University of California at Berkeley. A new algorithm is proposed based on complementation and the tautology check of a logic cover, derived from the PLA personality matrix. Both complementation and tautology check are performed by advanced logic manipulation algorithms used in the logic minimization program ESPRESSO II-C . The algorithm is exact, i.e., every testable crosspoint fault is tested, and maximum fault coverage is guaranteed. A quick preprocess, the biased random test generation, is used followed by the proposed algorithm to achieve the best balance between run time and test-set compactness. The program is refined at various stages by many powerful heuristics in the area of fault processing order, backend fault simulation, "don't-care" bit fixing, and on-the-fly test compaction. Both single stuck-at and crosspoint fault models are supported. PLATYPUS can also be used as a logic simulation tool and redundancy identifier. Test pattern generation has been performed by PLATYPUS on a large number of industrial PLA's.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:5 , Issue: 4 )
Date of Publication: October 1986