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Synthesis and Optimization of Multilevel Logic under Timing Constraints

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4 Author(s)
K. Bartlett ; Department of Electrical and Computer Engineering, University of Colorado at Boulder, Boulder, CO, USA ; W. Cohen ; A. De Geus ; G. Hachtel

The automation of the synthesis and optimization of combinational logic can result in savings in design time, significant improvements of the circuitry, and guarantee functional correctness. Synthesis quality is often measured in terms of the area of the circuit on the chip, which fails to take into account the timing constraints that might be imposed on the logic. This paper describes SOCRATES, a synthesis system capable of generating combinational logic in a given technology under user-defined timing constraints. We believe this system is the first to perform optimized, delay-constrained, multilevel synthesis into standard cell libraries. Applied to a large number of examples, the system has successfully traded off area versus delay and performs optimized, delay-constrained, multilevel synthesis into standard cell libraries.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:5 ,  Issue: 4 )