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Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits

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2 Author(s)
Ki Soo Hwang ; Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA ; Mercer, M.R.

In this paper, we analyze combinational logic circuits using "fan-out constraints" to generate tests for single stuck-at faults. A method of circuit transformation is employed to explicitly derive "fan-out constraints for controllability" and "fan-out constraints for observability," which are dependent Boolean functions and Boolen difference functions, respectively, in terms of primary inputs and fan-out stems. Then, a simplified version of a test generation algorithm which uses only the fan-out constraints for controllability at internal reconvergent fan-out stems is illustrated with an example. This approach differs from earlier work in that information about the circuit is accumulated and refined as the test generation process proceeds. In this test generation algorithm, the dependencies among fan-out nodes are ordered and solved in a hierarchical fashion so that the computation time for generating tests and detecting redundant faults can be greatly reduced--especially for locally redundant or "difficult" faults.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:5 ,  Issue: 4 )