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A global floorplanning approach is presented which allows designers to quickly explore layout issues during the initial stages of the IC design process. The approach is based on a combined mincut and slicing paradigm, in an effort to ensure routability. A slicing-tree representation is employed, upon which efficient traversal operations are applied resulting in area-efficient floorplans. The method allows modules to be specified as having a number of possible dimensions, and considers I/O pads as well as layout constraints. As a global improvement over previous floorplanning efforts, an in-place partitioning scheme is applied in conjunction with a combined exhaustive and heuristic bipartitioning approach. Moreover, a global channel routing and module I/O pin assignment scheme is used for floorplan evaluation, whereby module dimensions are chosen in conjunction with routing area, ensuring compact floorplans. A computer program, Mason, is presented which efficiently implements the approach and provides an interactive environment for designers to perform floorplanning. The performance of the program is discussed in terms of several industrial examples.