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Collecting Data About Logic Simulation

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2 Author(s)
R. D. Chamberlain ; Department of Computer Science and Electrical Engineering, Washington University, St. Louis, MO, USA ; M. A. Franklin

Design of high-performance hardware and software-based gate-switch-level logic simulators requires knowledge about the logic simulation process itself. Unfortunately, little data is publicly available concerning key aspects of this process. An example of this is the lack of published empirical measurements relating to the time distribution of events generated by such simulators. This paper presents a gate-switch-level logic simulator lsim which is oriented towards the collection of data about the simulation process. The basic components of lsim are reviewed, and its relevant data gathering facilities are discussed. An example is presented which illustrates the use of lsim in gathering data on event distributions and on communications requirements under alternative logic circuit partitionings.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:5 ,  Issue: 3 )