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A new electron beam tester, "FINDER" (Fault Identification system for LSI circuits with a Noncontacting Database-oriented Electron beam testeR), has been developed. This tester can automatically pinpoint faulty gates in logic VLSI circuits. It consists of a Scanning Electron Microscope (SEM) and an LSI Computer-Aided Design (CAD) system in a host computer. A logic-state image is observed from the surface of an LSI circuit being tested with the SEM. In addition, corresponding interconnection patterns superimposed with simulated logic states are obtained from the CAD system. Both images are matched automatically in the host computer, and the observed logic state for every interconnection pattern is then checked. Faulty gates can be pinpointed by tracing nodes with incorrect logic states on a logic circuits.