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A Methodology for Worst-Case Analysis of Integrated Circuits

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3 Author(s)
S. R. Nassif ; Department of Electrical and Computer Engineering, Research Center for Computer-Aided Design, Carnegie-Mellon University, Pittsburgh, PA, USA ; A. J. Strojwas ; S. W. Director

Worst-case analysis is one of the most often used techniques for verifying that the sensitivity of integrated circuit (IC) performances to changes in manufacturing conditions is minimized. However, worst-case analysis is often carried out in terms of a correlated set of parameters, which results in a design that is unnecessarily pessimistic. This paper presents a new approach to the worst-case analysis of integrated circuits that results in more realistic estimates of variations in device and circuit performances. In particular, worst-case analysis is performed in terms of a set of statistically independent process disturbances. A software package for worst-case analysis is described and illustrated by a number of examples. The results of the proposed worst-case analysis method are compared to Monte Carlo simulations.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:5 ,  Issue: 1 )