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An MOS depletion device model that is compatible with SPICE circuit simulation program and based on device physics is described. The depletion device is modeled by an equivalent circuit consisting of various well-characterized semiconductor devices, for example, the enhancement MOS device and the JFET. IT has the advantages of both the existing physical and empirical models. The model is applicable to immediate circuit simulation and device fabrication. Derivation of the model along with its parameters for the Gaussian impurity distribution is given. Implementation of circuit simulation with SPICE is demonstrated. More accurate results compared to the empirical model are obtained.